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INTEGRATED CIRCUITS
74LV175 Quad D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data of 1997 Feb 19 IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
FEATURES
* Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Four edge-triggered D flip-flops * Output capability: standard * ICC category: MSI
Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV175 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT175. The 74LV175 has four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All Qn outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn, Qn MR to Qn, Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VCC = 3.3 V VI = GND to VCC1 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 16 14 77 3.5 32 UNIT ns ns MHz pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD VCC2 fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV175 N 74LV175 D 74LV175 DB 74LV175 PW NORTH AMERICA 74LV175 N 74LV175 D 74LV175 DB 74LV175PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
PIN CONFIGURATION
MR Q0 Q0 D0 D1 Q1 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC Q3 Q3 D3 D2 Q2 Q2 CP
PIN DESCRIPTION
PIN NUMBER 1 2, 7, 10, 15 3, 6, 11, 14 4, 5, 12, 13 8 9 16 SYMBOL MR Q0 to Q3 Q0 to Q3 D0 to D3 GND CP VCC FUNCTION Master reset input (active LOW) Flip-flop outputs Complementary flip-flop outputs Data inputs Ground (0 V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
SV00596
1998 May 20
2
853-1926 19422
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
LOGIC SYMBOL (IEEE/IEC)
9 1 4 5 12 13 C1 R 1D 2 3 7 6 10 11 15 14
FUNCTIONAL DIAGRAM
4 D0 Q0 Q0 5 D1 FF0 to FF3 Q1 Q1 Q2 Q2 Q3 13 D3 MR 1 Q3 CP 2 3 7 6 10 11 15 14
12
D2
SV00601
9
LOGIC SYMBOL
9 4 D0 CP Q0 Q0 5 D1 Q1 Q1 Q2 Q2 Q3 13 D3 MR 1 Q3 2 3 7 6 10 11 15 14
SV00602
12
D2
SV00600
LOGIC DIAGRAM
D0 D1 D2 D3
D FF0 CP RD
Q
D FF1
Q
D FF2
Q
D FF3
Q
Q
CP RD
Q
CP RD
Q
CP RD
Q
CP MR
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
SV00603
FUNCTION TABLE
OPERATING MODES Reset (clear) Load `1' Load `0' INPUTS MR L H H CP X Dn X h l Qn L H L OUTPUTS Qn H L H
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition = LOW-to-HIGH clock transition X = don't care 1998 May 20 3
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - TYP 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C
tr, tf
Input rise and fall times
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC IIK IOK IO IGND, ICC Tstg PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with -standard outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +4.6 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C
Pt t tot
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 20
4
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V VIL LOW l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V; VI = VIH or VIL; -IO = 100A VO OH HIGH level output voltage; all outputs VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; STANDARD outputs VCC = 3.0V; VI = VIH or VIL; -IO = 6mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VO OL LOW level output voltage; all outputs VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage; STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
II ICC ICC
VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC - 0.6V
1.0 20.0 500
1.0 160 850
A A A
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 May 20
5
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1KW SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH / Propagation delay g y CP to Qn, Qn 2.0 Figures 1 2.7 3.0 to 3.6 1.2 tPHL/tPLH / Propagation delay g y MR to Qn, Qn 2.0 Figures 2 2.7 3.0 to 3.6 2.0 tw Clock pulse width C HIGH or LOW Figures 1 2.7 3.0 to 3.6 2.0 tw Master reset pulse width LOW Figures 2 2.7 3.0 to 3.6 1.2 trem Removal time MR to CP 2.0 Figures 2 2.7 3.0 to 3.6 1.2 tsu Set-up time Dn to CP 2.0 Figures 3 2.7 3.0 to 3.6 1.2 th Hold time Dn to CP 2.0 Figures 3 2.7 3.0 to 3.6 2.0 fmax Maximum clock ulse pulse frequency Figures 1 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C. 2. Typical values are measured at VCC = 3.3 V. 5 5 14 19 24 0 02 40 58 702 5 5 12 16 20 MHz 5 16 13 2 12 -5 -1 5 ns 19 15 22 5 5 -15 -122 5 2 26 ns 5 5 5 34 25 20 34 25 20 23 172 14 10 82 14 9 72 -60 -20 5 ns 43 34 41 30 24 41 30 24 ns ns 51 41 25 192 90 31 58 70 ns 48 38 56 45 MIN LIMITS -40 to +85 C TYP1 100 34 65 77 ns MAX -40 to +125 C MIN MAX UNIT
1998 May 20
6
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V; VM = 0.5 V x VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load.
VI CP INPUT GND tW tPHL VOH Qn OUTPUT VOL tPLH VOH Qn OUTPUT VOL VM tPHL VM tPLH GND VOH Qn OUTPUT VOL VOH Qn OUTPUT VM VM VM 1/fmax VI Dn INPUT VM VI CP INPUT GND tsu th tsu th VM
SV00604
VOL The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock (CP) to outputs (Qn, Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
SV00606
Figure 3. Data set-up and hold times for data input (Dn).
VI MR INPUT GND tW trem VI CP INPUT GND tPHL VOH Qn OUTPUT VOL VOH tPLH VM VM PULSE GENERATOR RT VI D.U.T. 50pF CL RL = 1k VO VM
TEST CIRCUIT
VCC
Test Circuit for switching times DEFINITIONS
VM
Qn OUTPUT VOL
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. TEST tPLH/tPHL VCC < 2.7V 2.7-3.6V VI VCC 2.7V
SV00605
Figure 2. Master reset (MR) pulse width, the master reset to outputs (Qn, Qn) propagation delay and master reset to clock (CP) removal time.
SV00901
Figure 4. Load circuitry for switching times.
1998 May 20
7
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 May 20
8
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 May 20
9
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 May 20
10
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 May 20
11
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
NOTES
1998 May 20
12
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74LV175
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04434
Philips Semiconductors
1998 May 20 13

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